1. Field of the Invention
The present invention relates to semiconductor apparatuses and method of making such apparatuses. More particularly, the invention relates to a semiconductor apparatus having a built-in electric coil and a method of making the semiconductor apparatus.
2. Discussion of the Background
As miniaturization of electronic equipment is advanced, power source apparatuses such as a step-up DC-DC converter for supplying power to such equipment are miniaturized, particularly into a low-profile package. FIG. 1 shows a block diagram of an exemplary circuit applied to a background step-up DC-DC converter 101. As shown in FIG. 1, the background step-up DC-DC converter 101 includes an IC component 103, an electric coil 105, a Schottky diode 107, and capacitors 109 and 111. It also includes a circuit board (not shown) having a circuit pattern therein for electrically connecting these components to each other. The IC component 103, which is a semiconductor apparatus, includes a switch 113 including an N-channel field-effect transistor (FET) and a control circuit 115 for controlling the switching operations of the switch 113.
The step-up DC-DC converter 101 charges an energy in the electric coil 105 when the switch 113 is turned on, and discharges the energy from the electric coil 105 by overlaying the energy on an input voltage (Vin) when the switch 113 is turned off. Thus, an output voltage (Vout) higher than the input voltage (Vin) is output. The control circuit 115 adjusts a time ratio of the switch 113 to make the output voltage (Vout) constant. The time ratio is a ratio of a time period when the switch 113 is turned on to a full cycle of the switching operation of the switch 113.
Some DC-DC converters are increasingly required to be driven at a frequency of 1 MHz or greater to achieve a miniaturization of the apparatus, as often required to those for small-sized electronic equipment. Under the circumstances, the electric coil is one of key factors and is needed to satisfy requirements of a small size, a superior frequency characteristic, and an appropriate electrical power capacity.
Recently, a low-profile and miniaturized IC chip has been developed with the advent of a wafer-level chip size package (CSP) technique with which pads in an array form are prepared on a wafer before the IC components are cut up. For example, Japanese Laid-Open Patent Application Publication, No. 2000-260910, describes the wafer-level CSP.
Referring to FIG. 2, a background manufacturing method with respect to the wafer-level CSP is explained. As shown in FIG. 2, in the background manufacturing method, a base insulating film 3 is formed on a semiconductor substrate 1 and a semiconductor element (not shown) such as a transistor is formed therein. After that, a lower insulating layer 5 composed of a boro-phospho silicate glass (BPSG) film is formed relative to the entire surface of the semiconductor substrate 1. The lower insulating layer 5 is provided with a plurality of connection holes (not shown) therein. Then, the lower insulating layer 5 is provided with an Al distribution (not shown) and an Al electrode pad 23.
The lower insulating layer 5 and the Al electrode pad 23 are covered by a passivation film including a phospho silicate glass (PSG) film 9 as a lower layer and a silicon nitride (SiN) film 11 as an upper layer. The passivation film comprising PSG film 9 and SiN film 11 is one of inter-layer insulating layers. Further, a polyimide layer 16 is formed on the passivation film comprising PSG film 9 and SiN film 11. A pad opening 25 is formed in the insulating layer above the Al electrode pad 23 in order to have an electrical connection with a metal distribution layer formed in a later process and to allow a probe to contact the Al electrode pad 23 during a wafer test in a later process.
Then, in the background manufacturing method, the wafer test is performed in which the probe is contacted with the Al electrode pad 23.
A barrier metal layer 18 comprising chromium and an electrode layer comprising copper for soldering (not shown) are formed relative to the entire surface of the semiconductor substrate 1, by a sputtering deposition. The barrier metal layer 18 is located between a copper-comprising metal distribution layer formed in a later process and the Al electrode pad 23 to prevent mutual invasion at that location.
A photoresist pattern (not shown) is formed over a predetermined region on the electrode layer. Subsequently, a Cu distribution layer 27 and a Cu electrode pad 29 are formed by soldering and electrolytic plating. The Cu distribution layer 27 and the Cu electrode pad 29 are referred to as a redistribution layer. Conventionally, the redistribution layer generally comprises copper because copper provides high mechanical strength and high reliability in terms of moisture resistance.
After removal of the photoresist pattern, unnecessary portions of the soldering electrode layer and the barrier metal layer 18 are removed with masks of the Cu distribution layer 27 and the Cu electrode pad 29 using a wet etching. Then, a metal layer is formed by sputtering deposition and electrolytic plating. Subsequently, the metal layer is patterned by photoengraving and etching to form a metal post 31 on the Cu electrode pad 29.
Then, the wafer, an encapsulation resin 21, and a temporal film (not shown) are placed in a mold tool (not shown) for encapsulation with the encapsulating resin 21. The temporal film is a material for preventing contact of the encapsulating resin 21 to the mold tool. Then, heat and pressure are applied to the mold tool to an extent that the metal post 31 is projected from an encapsulating resin 21. Subsequently, a barrier metal layer 33 is formed on the surface of the metal post 31. Then, a solder sphere 35 is mechanically fixed to the metal post 31 of the wafer encapsulated by the encapsulating resin 21, through the barrier metal layer 33. As a final process, the wafer is cut up into individual chips.
Because of resin encapsulation at the wafer level, the number of manufacturing processes is reduced and miniaturization of chip size is achieved.
However, the background DC-DC converter still has a thick profile even though the IC component of the DC-DC converter is made thin. This is because the electric coil in the background DC-DC converter is fixed to the rear surface of the circuit substrate. In addition, there is a certain limit in making the circuit substrate thin and therefore it is difficult to further make a power source device, such as the DC-DC converter, thin.